`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/04/12 16:02:37
// Design Name: 
// Module Name: clk_32div
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clk_32div(
    input clk,
    input rst,
    output reg clk_32div

    );
    
reg [3:0] cnt_16;
always@(posedge clk)begin
    if(rst)begin
        cnt_16<=4'd0;
    end
    else begin
        if(cnt_16==4'd15)begin
            cnt_16<=4'd0;
        end
        else begin
            cnt_16<=cnt_16+1'd1;
        end
    end
end

always@(posedge clk)begin
    if(rst)begin
        clk_32div<=1'd0;
    end
    else begin
        if(cnt_16==4'd15)begin
            clk_32div<=~clk_32div;
        end
        else begin
            clk_32div<=clk_32div;
        end
    end
end

endmodule
